Current mirror having a high output voltage

ABSTRACT

A current mirror comprises a first branch in which a current to be duplicated (IE) flows and which comprises the main current path of a first transistor (T 1 ), and a second branch in which the output current (Is), which is a replica of the input current, flows and which comprises the main current path of a second transistor (T 2 ). 
     In order to obtain a higher maximum output voltage the main current path of a transistor is arranged in the second branch in series with that of the second transistor. 
     The bases of the first and second transistors are interconnected. A current I B  is injected into the base of the series transistor and, if required, into the first branch. The current I B  is suitably obtained by dividing a current 2I B  derived from the base current I B  of the first and second transistors.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a current mirror comprising a first branch forreceiving an input current to be reproduced, which first branchcomprises the main current path of a first transistor of a firstconductivity type, and a second branch for supplying an output currentwhich is a replica of the input current, which second branch comprisesthe main current path of a second transistor of the first conductivitytype, the bases of the first and the second transistor beinginterconnected, a third transistor of the first conuductivity typehaving its base and collector connected respectively to the collectorand the base of the first transistor.

2. Description of the Prior Art

A current mirror of the type defined in the opening paragraph is knownas a WIDLAR-type current mirror, in which the collector of the thirdtransistor is connected to a power-supply source.

In an arrangement of this type the output voltage is limited toapproximately B_(VCEO), which is the value beyond which the secondtransistor operates in the avalanche-breakdown region.

SUMMARY OF THE INVENTION

It is the object of the invention to provide a current mirror whichenables substantially higher output voltage to be obtained.

To this end it is characterized in that the second branch comprises themain current path of a fourth transistor of the first conductivity typein series with the main current path of the second transistor, and inthat it comprises an auxiliary current mirror for injecting into thebase of the fourth transistor a first injection current equal to halfthe current flowing in the collector of the third transistor.

In a preferred embodiment the auxiliary current mirror may comprise afifth transistor of a second conductivity type opposite to the firstconductivity type, having a first collector for supplying said firstinjection current and a second collector, constituted for example by twointerconnected collector portions of the same surface area as the firstcollector, which second collector is connected to the base of the fifthtransistor and to the collector of the third transistor.

In a first embodiment the current mirror supplies a second injectioncurrent of the same value as the first injection current, which secondinjection current is added to said input current in the first branch.The second injection current can be supplied by a third collector of thefifth transistor.

In a preferred second embodiment, which enables the occurrence of theEarly effect in the second transistor to be minimized the first branchcomprises the main current path of a sixth transistor of the firstconductivity type between the emitter of the first transistor and thecommon mode terminal, which sixth transistor has its collector connectedto the emitter of the first transistor and its emitter to thecommon-mode terminal, and the output branch comprises a diode poled inthe forward direction and having one electrode connected to thecommon-mode terminal. The diode may be, for example, a diode-connectedseventh transistor of the first conductivity type, whose base andcollector are short-circuited and connected to the base of the sixthtransistor and to the emitter of the second transistor, the emitter ofthe seventh transistor being connected to the common-mode terminal.

Suitably, for example by providing the fifth transistor with a fourthcollector, the auxiliary current mirror is adapted to supply a thirdinjection current which has the same value as the first one and which isadded to the current supplied by the main-current path of the fourthtransistor in the second branch.

In a third embodiment, by means of which higher voltages than in the twopreceding cases can be obtained, the second branch comprises the maincurrent path of an eighth transistor of the first conductivity typebetween the collector of the fourth transistor and the point where theoutput current is available, the auxiliary current mirror being adaptedto inject a fourth injection current of the same value as the firstinjection current into the base of the eighth transistor, for example bythe providing the fifth transistor with a fifth collector. The fifthtransistor may also comprise a sixth collector supplying a fifthinjection current which has the same value as the collector current ofthe third transistor and which in the first branch is added to saidinput current.

Embodiments of the invention will now be described in more detail, byway of example, with reference to the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1a shows a known current mirror of the WIDLAR type,

FIG. 1b shows a known current mirror of the WILSON type,

FIG. 2 shows a first embodiment of a current mirror in accordance withthe invention,

FIG. 3 shows a preferred embodiment of a current mirror in accordancewith the invention, which mitigates the influence of the Early effect,and

FIG. 4 shows a third embodiment of the invention having a very highoutput voltage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In FIG. 1a a current mirror of the WIDLAR type comprising an inputbranch which receives an input current I_(E) and which comprises themain current path of a transistor T₁, and an output branch, in which anoutput current Is flows and which comprises the main current path of atransistor T₂. The base of the transistors T₁ and T₂ are interconnected.A transistor T₃ has its base connected to the point to which the currentI_(E) is applied and its main current path is arranged between apower-supply source U and the bases of the transistors T₁ and T₂. In thepresent case the transistors T₁, T₂ and T₃ are of the npn type, theemitters of T₁ and T₂ being connected to the common-mode (or ground)terminal and the emitter of T₃ being connected to the bases of T₁ andT₂. Since the base current of the transistor T₃ is negligible, theoutput current Is is equal to the input current I_(E).

In FIG. 1b a current mirror of the WILSON type comprises an inputbranch, receiving an input current I_(E) and comprising the main currentpath of a transistor T'₁, and an output branch, in which an outputcurrent I_(s) flows and which comprises the main current path of atransistor T'₂.

Moreover, in series with the main current path of the transistor T'₁ thefirst branch comprises a diode D₁, which is poled in the forwarddirection and which is here represented as an npn-transistor whose baseand collector are short-circuited and connected to the base of thetransistor T'₂ and whose emitter is connected to the collector of thetransistor T'₁, whose emitter is connected to the common-mode terminal.

In addition, the second branch comprises a diode D₂ in series with themain current path of the transistor T'₂, which diode is poled in theforward direction and which is here represented as an npn transistorwhose base and collector are short-circuited and connected to the baseof the transistor T'₁ and to the emitter of the transistor T'₂, andwhose emitter is connected to the common-mode terminal.

I_(B1) and I_(B2) are the base currents of the transistors T'₁ and T'₂respectively.

The current applied to the collector of T'₁ has the value I_(E) -I_(B2),so that the current flowing in the emitter of T'₁ has the value I_(E)-I_(B2) +I_(B1). As a result of the interconnection between the base ofthe transistor T'₁ and the anode of the diode D₂, the latter current isequal to that flowing in the diode D₂ if it is assumed that this diodeis a diode-connected transistor of the same dimensions as the transistorT₁ '.

The current, I_(s) +I_(B2), which flows in the emitter of the transistorT'₂ consequently has the value I_(E) -I_(B2) +2 I_(B1), so that:

    I.sub.s =I.sub.E +2(I.sub.B1 -I.sub.B2)≃I.sub.E

However, the structure of the output branch limits the maximum outputvoltage which can be obtained on the collector of the transistor T₂(FIG. 1a) or T'₂ (FIG. 1b) to a value of the order of magnitude ofB_(VCEO) +V_(BE), because when the collector-emitter voltage of T₂reaches the value B_(VCEO), which is the collector-emitter avalanchevoltage, its operation is no longer linear and Is is then only anapproximation to I_(E).

For certain uses a reproduction accuracy of the order of a few % isdesirable, which means that the arrangement must be redesigned.

The basic idea of the invention is to arrange the two main current pathsof two transistors in series in the output branch in such a way that asubstantially higher output voltage can be obtained, for example of theorder of 2 B_(VCEO), while preserving the reproduction accuracy of theinput current I_(E).

In FIG. 2 the input branch receiving the input current I_(E) comprisesthe main current path of a transistor T₁ whose emitter is connected tothe common-mode terminal.

The main current paths of the transistors T₂ and T₄ are arranged inseries in the output branch supplying the current I_(s), the emitter ofT₄ being connected to the collector of T₂ and the emitter of T₂ beingconnected to the common-mode terminal. Moreover, the bases of thetransistors T₁ and T₂ are interconnected, as a result of which the twotransistors have equal emitter currents.

In the two branches equal currents are obtained by injecting currents ofthe same value I_(B) into the base of the transistor T₄ and into thefirst branch, so that the latter current is added to the input currentI_(E).

In the embodiment shown in FIG. 2 said currents are supplied by amulti-collector transistor T₅ having four collector outputs. One ofthese collector outputs is used for injecting a current I_(B) into theinput branch in such a way that it is added to the input current I_(E)(enabling exact compensation to be obtained) and another collectoroutput is used for injecting a current I_(B) into the base of thetransistor T₄. The remaining two collector outputs are interconnectedand connected to the base of the transistor T₅, the resulting current2I_(B) being due to equal halves contributed each of said remaining twocollectors. Thus, the transistor T₅ constitutes an auxiliary currentmirror. This current 2I_(B) is the collector current of a transistor T₃having its emitter connected to the base of the transistors T₁ and T₂and having its base connected to the collector of the transistor T₁. Theemitter of the transistor T₅ receives a supply voltage U.

Since the transistors T₄ and T₂ have practically the same collectorcurrent, and their base current I_(B) is the same, they will havesubstantially the same collector-emitter voltage.

Vs is the output voltage on the collector of the transistor (point S).The voltage V_(A) on point A (the collector of T₂) is then substantiallyequal to 1/2 Vs.

This division of the output voltage between the two transistors T₂ andT₄ enables the maximum output voltage to be substantially doubledrelative to a single current mirror. A distinction can be made betweentwo ranges of operation.

(1) Vs <2U-2 V_(BE), V_(BE) being a base-emitter voltage of a transistor(approximately 0.7 V). If U<B_(VCEO), this yields V_(A) =Vs/2<U-V_(BE)so that V_(A) <B_(VCEO)

In this range T₂ and T₄ both operate in their linear region. It is to benoted that since V_(A) varies the transistor T₂ will exhibit a certainsusceptibility to the Early effect.

(2) 2 U-2 V_(BE) <Vs<U+B_(VCBO)

The transistor T₅ is bottomed and V_(A) is stabilized at U-V_(BE).

A current I_(B) can reach the collector-base junction of the transistorT₄, which transistor will then begin to operate in the range BV_(CB).This means that:

    I.sub.S =I.sub.E +|I.sub.B |

This current I_(B) increases as V_(S) increases. The limit value of Vsis U+BV_(CBO) or the BV_(CS) of the transistor T₄.

Example:

    ______________________________________                                        BV.sub.CEO = 27 V                                                                           BV.sub.CBO = 67 V                                                                         BV.sub.CS = 80 V                                    I.sub.E = 100 μA                                                           ______________________________________                                    

U=25 V; 1-kΩ resistors are arranged in the emitter lines of T₁ and T₂.

    __________________________________________________________________________    Vs(V)                                                                             1  5   10  20  30  50  60  70  79                                         __________________________________________________________________________    Is(μA)                                                                         99.64                                                                            100.42                                                                            101.12                                                                            102.34                                                                            102.83                                                                            104.12                                                                            106.73                                                                            115.34                                                                            150                                        __________________________________________________________________________

In FIG. 3 the transistors T₁ . . . T₅ are arranged in the same way as inFIG. 2, except that the collector of the transistor T₅ which injects acurrent into the input branch has been dispensed with.

Between the emitter of the transistor T₁ and the common-mode terminalthe input branch comprises the main current path of a transistor T₆,whose collector is connected to the emitter of the transistor T₁ andwhose emitter is connected to the common-mode terminal.

The output branch comprises a diode-connected transistor T₇ which hasits base and its collector shortcircuited and connected to the base ofthe transistor T₆ and to the emitter of the transistor T₂. The emitterof the transistor T₇ is connected to the common-mode terminal. Thismeans that: Is=I_(E) +I_(B) (equal currents in the transistors T₆ andT₇) with Vs≧2 B_(BE) ≈1.5 V.

This means that the susceptibility to the Early effect is reduced.

Example:

    U=25 V, I.sub.E =100 μA

BV_(CEO), BV_(CBO), B_(VCS) have the same values as in the foregoingexample.

    __________________________________________________________________________    Vs(V)                                                                             1.5                                                                              5   10  20  30  50  60  70  81                                         __________________________________________________________________________    Is(μA)                                                                         99.81                                                                            100.04                                                                            100.13                                                                            100.39                                                                            100.66                                                                            101.88                                                                            104.47                                                                            112.87                                                                            150                                        __________________________________________________________________________

The accuracy is very high from 1.5 V to 50 V and subsequently degradesrapidly.

In FIG. 4 the output branch comprises, in this order, the main currentpaths of the transistors T₈, T₄ and T₂ in series with the point Ssupplying the output current Is. To simplify the drawing, the transistorT₅ is represented as two transistors T₅₁ and T₅₂ having their basesinterconnected and having their emitters connected to the power-supplysource U. The transistor T₅₁ has two collectors connected to therespective bases of the transistors T₈ and T₄. The transistor T₅₂ hasfour collectors of the same surface area interconnected pairwise (or twocollectors of twice the surface area of those of the transistor T₅₁).Two of said interconnected collectors are connected to the point of theinput branch which receives the current I_(E), in such a way that theircurrent is added to said input current. The two other interconnectedcollectors are connected to the base of the transistor T₅₂ and to thecollector of the transistor T₃, if desired via a Zener diode which ispoled in the reverse direction and whose Zener voltage is suitablyhigher than U-BV_(CEO) (T₃), in order to minimise the risk of breakdown.A current I_(B) flows in the bases of the transistors T₁ and T₂ so thata current 2I_(B) flows in the collector of the transistor T₃ if the basecurrent of this transistor is ignored. The transistors T₅₁ and T₅₂,which constitute a current mirror similar to that comprising thetransistor T₅, supplies a current 2I_(B) to the input branch and acurrent I_(B) to the base of each of the transistors T₈ and T₄. Acurrent I_(E) +3I_(B) flows in the emitters of T₁ and T₂, a currentI_(B) +2I_(B) in the emitter of T.sub. 4, and a current I_(E) +I_(B) inthe emitter of T₈, so that Is is a replica of the input current I_(E).

If U=2BV_(CEO) the voltage V_(s) can reach a value of approximately 3BV_(CEO), i.e. approximately 80 V if the values of the precedingexamples are adopted.

What is claimed is:
 1. A current mirror comprising a first branch forreceiving an input current to be reproduced, which first branchcomprises a main current path of a first transistor of a firstconductivity type, and a second branch for supplying an output currentwhich is a replica of the input current, which second branch comprises amain current path of a second transistor of the first conductivity type,bases of the first and the second transistor being interconnected, athird transistor of the first conductivity type having its base andemitter connected respectively to a collector and a base of the firsttransistor, characterized in that the second branch comprises a maincurrent path of a fourth transistor of the first conductivity type inseries with the main current path of the second transistor and in thatit comprises an auxiliary current mirror for injecting into the base ofthe fourth transistor a first injection current equal to half thecurrent flowing in the collector of the third transistor.
 2. A currentmirror as claimed in claim 1, characterized in that the auxiliarycurrent mirror comprises a fifth transistor of a second conductivitytype 1 opposite to the first conductivity type, having a first collectorfor supplying said first injection current and a second collectorconnected to a base of the fifth transistor and to the collector of thethird transistor.
 3. A current mirror as claimed in claim 2,characterized in that the second collector of the fifth transistorcomprises two interconnected collector portions of the same surface areaas the first collector.
 4. A current mirror as claimed in claim 2,characterized in that the auxiliary current mirror is adapted to supplya second injection current of the same value as the first injectioncurrent, which second injection current is added to said input currentin the first branch.
 5. A current mirror as claimed in claim 4,characterized in that the fifth transistor has a third collector forsupplying the second injection current.
 6. A current mirror as claimedin claim 2, characterized in that the first branch comprises a maincurrent path of a sixth transistor of the first conductivity typeconnected between the emitter of the first transistor and a common-modeterminal, which sixth transistor has its collector connected to theemitter of the first transistor and its emitter to the common-modeterminal, and in that the second output branch comprises a diode poledin the forward direction, which diode has one electrode connected to thecommon-mode terminal and its other electrode to an emitter of the secondtransistor and to the base of the sixth transistor.
 7. A current mirroras claimed in claim 6, characterized in that said diode comprises aseventh transistor of the first conductivity type having its base andcollector short-circuited and connected to the base of the sixthtransistor and to the emitter of the second transistor, the emitter ofthe seventh transistor being connected to the common-mode terminal.
 8. Acurrent mirror as claimed in claim 6, characterized in that theauxiliary current mirror is adapted to supply a third injection currentwhich has the same value as the first one and which is added to thecurrent supplied by the main-current path of the fourth transistor inthe second branch.
 9. A current mirror as claimed in claim 8,characterized in that the fifth transistor has a fourth collector forsupplying said third injection current.
 10. A current mirror as claimedin claim 2, characterized in that said second branch comprises the maincurrent path of a sixth transistor of the first conductivity typeconnected between a collector of the fourth transistor and a point forsupplying the output current, and in that the auxiliary current mirroris adapted to inject a second injection current of the same value as thefirst injection current into a base of the sixth transistor.
 11. Acurrent mirror as claimed in claim 10, characterized in that theauxiliary current mirror is adapted to supply a third injection currentof the same value as the collector current of the third transistor, saidthird injection current being added to said input current in the firstbranch.
 12. A current mirror as claimed in claim 10, characterized inthat the fifth transistor has a third collector for supplying the secondinjection current.
 13. A current mirror as claimed in claim 12,characterized in that the fifth transistor has a third collector forsupplying the third injection current.
 14. A current mirror as claimedin claim 13, characterized in that the third collector comprises twointerconnected collector portions having the same surface area as thatof the second collector.
 15. A current mirror as claimed in claim 10further comprising a Zener diode which is poled in the reverse directionand connected in a collector line of the third transistor, said Zenerdiode having a Zener voltage which is at least equal to the supplyvoltage minus the avalanche voltage of a transistor.
 16. A currentmirror as claimed in claim 1, characterized in that the auxiliarycurrent mirror is adapted to supply a second injection current of thesame value as the first injection current, which second injectioncurrent is added to said input current in the first branch.
 17. Acurrent mirror as claimed in claim 1, characterized in that said secondbranch comprises the main current path of a sixth transistor of thefirst conductivity type connected between a collector of the fourthtransistor and a point for supplying the output current, and in that theauxiliary current mirror is adapted to inject a second injection currentof the same value as the first injection current into a base of thesixth transistor.